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| ZMD44101 single-chip 868mhz to 928mhz rf transceiver introduct i on key featu r es description cop y right ? 200 5, zmd a g data sheet - mar c h 2005 the zmd441 01 is a fully in tegrated syst em-o n-chi p cmos tra n sceiver, p r ovi d ing licen se free multi- cha nnel ope ration in th e 868.3m hz (eu) an d 902m hz to 928m hz (us ) ism ba nd s. the l o w power ba se b and tran sceiv e r is optimi z ed for data rates up to 40kb p /s a nd incorporates di re ct seq uen ce sp read spe c tru m tech nolo g y to assure reliabl e data transfe r in h o stile rf en vironme n ts. the hi gh l e vel of inte gration, sh o w n belo w , inclu d e s a thi n media a ccess controll e r , re sulting in a minimu m of externa l comp one nts and l o we r appli c ation co sts. ieee 802.15.4 compli ant ism band tran sceiver with rf and baseba nd dire ct sequ e n ce sp rea d spectrum (ds ss) burs t data rat e 20kbit/s (e u), 40k b it/s (us) tran smit ra n ge up to 100 meter (los) low p o wer fo r battery ope rated devices spi and para llel interfaces compli ant phy and thi n mac available in 48-le ad qf n (7mm x 7mm) packa ge applications operating reference data energy man a gement tempe r atu r e ran ge? ?? ?.?-4 0 c to +85 c remote m e te ring an d co ntrol supply voltage, v dd ?????? ?? ?.+2.4 v home a nd bu ilding control typic a l supply current (tx ac tive)??.....32ma industri a l net w orks typic a l supply current (rx ac tive)??.....28ma remote key l es s entry (tw o -w ay ) typic a l supply current (s leep mode)...... .... .2a health mo nitor net w o r ki n g freq uen cy range ??? ?.868m hz to 928mhz a i rf ra m i n g e r ro r d e t e c t i o n ( c r c ) d u ty cy cle h o s t i n te r f ac e thi n h w -m a c comp lete phy a n a l og digital a n al o g r e c e i v er pl l a n al o g t r an s m i t t e r digital r x 1) sy n c hron i z at i o n 2) desp r e ad i n g 3) dem o d u la tion 4) di gi t a l fi lte r in g di gi ta l t x 1) sp r e ad ing 2) pu lse s h a p ing dedic a ted d s p f unctions a ddition a l ma c f unctions pr ot o c ol i m pl em en ta t i on net w ork su pp ort upper l a y e r f unctionali t y ap plicatio n i n t e rf a c e s (s e n s o r) a pplic ati on spe c i f ic con t ro l l e r/ sen s or sp i o r pa rall el regi ste r s z m d 44 10 1 24 m h z 3 2 . 76 8k hz p l l rc- lpf po w e r m a nager all rights reserved. the material contai ned herein may not be rep r oduced, adapte d , merged, trans lated, stored, or used w i thout the prior written consent o f the cop y right o w n e r. the inform ation furnis hed in this publication is prelim inar y and subject to changes w i t hout n o tice.
ZMD44101 single-chip 868mhz to 928mhz rf transceiver preliminary - march 2005 information is current as of publication date. products conform to specification per the terms of the zmd standard warranty. production testing does not necessarily include testi ng of all parameters. copyright ? 2004, zmd ag table of contents 1 pin diag ram .................................................................................................................... ................ 3 2 general device specifications .................................................................................................. ...... 4 2.1 absolute maximu m ratings ................................................................................................... 4 2.2 recommended operati ng conditions .................................................................................... 4 2.3 d.c. electrical characteristics ................................................................................................ 4 2.4 digital i/o .................................................................................................................... ............ 5 3 a.c. electrical characteristics ................................................................................................ ........ 5 3.1 general ........................................................................................................................ ........... 5 3.2 startup time ............................................................................................................................ 5 4 interf aces ..................................................................................................................... ................... 6 4.1 overview ....................................................................................................................... ......... 6 4.2 serial peripheral interface (spi) ............................................................................................ 7 4.2.1 spi confi guration .............................................................................................................. .7 4.3 parallel in terfac e .................................................................................................................... 9 5 registers ...................................................................................................................... ................. 10 5.1 mac control + stat us register ............................................................................................... 10 5.2 mac timing r egisters ........................................................................................................... .11 5.3 other mac r egisters ............................................................................................................ .12 5.4 mac header r egisters .......................................................................................................... 1 3 5.5 phy registers .................................................................................................................. ..... 13 6 application circuit ? ex ternal components .................................................................................... 14 7 ZMD44101 system perf ormance su mmary ................................................................................. 15 8 system desc ription ............................................................................................................. .......... 16 8.1 general block diagram ........................................................................................................ 16 8.2 receiver chain ................................................................................................................. .... 17 8.2.1 ragcl - agc level register ......................................................................................... 18 8.3 transmitte r chain .............................................................................................................. ... 18 8.3.1 rtxm - transmitte r mode regi ster ................................................................................. 18 8.4 rf phase lo cked lo op ........................................................................................................ 19 8.5 reference crystal os cillator (2 4mhz) .................................................................................. 20 8.6 low power crystal osc illator (32. 768khz) ........................................................................... 21 8.7 clko - clock output configur ation ..................................................................................... 21 8.8 power mana gement ............................................................................................................. 22 9 mechanical specifications ...................................................................................................... ....... 23 9.1 package ........................................................................................................................ ....... 23 10 list of abbr eviati ons .......................................................................................................... ............ 25 11 references ..................................................................................................................... ............... 25 ZMD44101 single-chip 868mhz to 928mhz rf transceiver preliminary - march 200 5 page 3 of 26 copyri ght ? 2 005, zmd ag 1 pin diagram figure 1.1 provides the pi n layout for the zmd4 410 1 and tabl e 1.1 the descripti on of the re sp ective pin s . zm d441 01 48 q f n (= m lf) t o p vi ew 1 48 12 13 24 25 36 37 wr rd dv d d _ 3 . 3 dvs s dv d d ale avd d av ss rtc1 rtc2 nc nc ss irq gpd d v dd_ 3 . 3 dv d d rs n dv d d nc nc av dd lp f 2 lp f 1 mo s i mi s o sck da [ 0 ] da [ 1 ] da [ 2 ] da [ 3 ] da [ 4 ] da [ 5 ] da [ 6 ] da [ 7 ] cl ko xt al 2 xt al 1 av d d rfo a vss rfio a vss av d d a vss av d d nc nc figure 1.1 - pin layout pin no. pin nam e pin ty p e des c ription pin no. pin nam e pin ty p e des c ription 1 n c - n o con n ecti o n 25 m o si c m os io spi i n t e r f ac e - m a ster out, sl av e i n 2 nc - no con n ectio n 26 m i so cm os io spi int e r f ac e - m a ster i n , slav e ou t 3 avd d avd d anal og p o w e r suppl y 27 sc k c m os io spi i n t e r f ac e - ser i al cl ock 4 avss gr ound anal og g r ound 28 d a 0 c m os io d a ta a d dr ess 5 a v dd a v dd rf p o w e r su p p ly 2 9 da 1 cmos io da ta ad d r e ss 6 avss gr ound r f g r ound 30 d a 2 c m os io d a ta a d dr ess 7 r f io r f io r f r e cei v er i nput a nd t r ansmi t t e r ou tpu t 31 d a 3 c m os io d a ta a d dr ess 8 avss gr ound r f g r ound 32 d a 4 c m os io d a ta a d dr ess 9 rfo rf outp ut rf tr ansmit t er o u tp ut 33 da5 cm os io data a d dr ess 10 avd d avd d anal og p ll pow er sup p l y 34 d a 6 c m os io d a ta a d dr ess 11 x t al1 analog in put 24mhz cr y s tal oscilla to r input 35 da7 cmos io data a d dress 1 2 xt a l 2 a n a l o g outp ut 2 4 m hz cr y s ta l o scilla tor o u t pu t 3 6 cl k o cmos ou tpu t clo ck (to e x te rn a l d e v i ce ) 1 3 l p f 1 anal og ou tpu t loo p f i l t er , c har g e - p u m p nod e 37 w r cm os io w r it e d a ta ad dr ess 1 4 l p f 2 anal og in p u t loo p f i l t er , vc o tu ne n ode 38 r d c m os io r ead dat a a d dr ess 15 avd d avd d anal og p ll vc o pow er suppl y 39 d v d d _3.3 d v d d _3.3 d i g i t al io 3.3v pow e r suppl y ( post- dr i v er ) 16 n c - n o con n ecti o n 40 d vss gr ound d i g i t al gr ound 1 7 nc - no co nn e c tion 41 d v d d d v d d d i g i t al cor e 2.4v pow e r suppl y ( c or e an d pr e- dr i v er ) 18 d v d d d v d d d i g i t al pll pow er sup p l y 42 ale c m os io addr ess l a tch en abl e 19 r s n c m os inp u t asy n chr onous chi p r e s e t ( l ow - acti v e ) 43 avd d avd d anal og p o w e r suppl y 20 d v d d d v d d d i g i t al cor e 2.4v pow e r suppl y ( c or e an d pr e- dr i v er ) 44 avss gr ound anal og g r ound 21 d v d d _3.3 d v d d _3.3 d i g i t al io 3.3v pow e r suppl y ( post- dr i v er ) 45 r t c 1 anal og in put 32.7 68kh z cr y s tal osci ll ator i n p u t 22 gpd c m os io gl obal p o w e r d o w n ( f r o m ex ter n al d e v i ce) ( h -acti v e) 46 r t c 2 anal og ou tpu t 32.7 68kh z cr y s tal osci ll ator ou tpu t 23 irq cm os outp ut inter r u p t ( t o ex ter n al de v i ce )(lo w a c t i v e ) 4 7 nc - no co n n e c t i on 24 ss c m os io spi i n t e r f ac e - sl av e sel e ct 48 n c - n o c o nn ecti o n table 1.1 - pin de sc ription s z m d4410 1 single-chip 868mhz to 928mhz rf transceiver p reliminar y - march 200 5 copyri ght ? 2 005, zmd ag page 4 of 26 2 general device specifications electri c al ch a r acte ri stics o v er full rang e of op erat in g con d ition s , typical value s are av dd, dvdd = 2.4v, dvdd_3.3 = 3.3 v, t a = 25 c, unle s s otherwise note d . 2.1 absolute maximum ratings cautio n: operation b e yo nd these values may ca u s e pe rma nen t damage to the device o r decrea s e in reliability. note: values are over free -ai r temperature unless otherwise noted. p a r a m e t e r s y m b o l m i n t y p m a x u n i t n o t e s analog sup p l y voltage avdd - - 3.5 v digital supply voltage dvdd - - 3.5 v digital io supply voltage dvdd_3.3 - - 4.6 v input voltage v i - - 6 v at cmos io output voltag e v o - - 4.6 v at cmos io analog input voltage v ana - - 3.5 v at analog io input rf lev el p in - - 2 0 d b m storage te m peratu r e t strg - 6 5 - 1 5 0 c esd protecti on v esd - - 2 kv hbm (10 0pf, 1.5k ? ) 2.2 recommended operating conditions p a r a m e t e r s y m b o l m i n t y p m a x u n i t n o t e s analog sup p l y voltage avdd 2.2 2.4 2.7 v digital supply voltage dvdd 2.2 2.4 2.7 v digital io supply voltage dvdd_3.3 3 .0 3.3 3.6 v ambient tem peratu r e t a - 4 0 + 2 7 + 8 5 c industri a l ra n g e freq uen cy of operation f op 8 6 0 9 3 0 m h z 868.3m hz (eu), 90 2mhz to 928mhz (us) 2.3 d.c. electrical characteristics note: values are for suppl y current. p a r a m e t e r s y mbol m i n t y p m a x u n i t sleep mod e (32khz cry s tal and timer on ) idd - 2 - a idle mode (24 m hz cry s tal o n ) idd - 1 - ma tran s m i t mod e i d d - 3 2 - m a re ceive mod e , synch r oni zation idd - 31 - ma re ceive mod e , normal idd - 28 - ma ZMD44101 single-chip 868mhz to 928mhz rf transceiver preliminary - march 2005 page 5 of 26 copyright ? 2005, zmd ag 2.4 digital i/o module s y mbol min t yp max unit notes cmos in p ut v il -0.3 0.8 v v ih 2 5.5 v cmos output v ol 0.4 v v oh 2.4 v 3 a.c. electrical characteristics electrical characteristics over full range of operat ing conditions, typical values are avdd, dvdd = 2.4v, dvdd_3.3 = 3.3 v, ta = 25 q c, unless otherwise noted. 3.1 general symbol min typ max unit note transmitter p out -3 0 3 dbm output power at 50 ? z m d4410 1 single-chip 868mhz to 928mhz rf transceiver p reliminar y - march 200 5 copyri ght ? 2 005, zmd ag page 6 of 26 di gi ta l c o re tx fif o 1 28x 8 rx fi fo 2 56x 8 in te r- f ace sp i paral- le l reg. ba nk miso mo s i sck ss ale rd wr d a [7 :0 ] ir q gpd spi c on f i g[ 5 : 0] s p itx [7 :0] s p is ta rt sp i r x[ 7: 0 ] 4 interfaces 4.1 overview figure 4-1: inter f ac e blo ck diagr a m the z m d441 01 p r ovide s a pa rallel inte rface an d an spi to acce ss the inte rnal re giste r b a n k , the tx a n d the rx fifo. additionally it has a irq o u tput and a d edicated glo b a l power do wn (gpd) input . by default bo th interfa c e s t he p a rall el a n d the spi a s slave are ava ilable. fo r proper op eratio n the unu se d interface sh all be disable d . the pa rallel interface i s di sabl ed by setting rd,wr, and a l e to h i gh, puttin g the dataadd r ess[7:0] bus i n to high -z st ate. the spi is disable d by setting ss to high. the spi can also b e co nfigure d as m a ster. in t he master setup i s behave s like a remote inte rface whi c h can b e controlled by the exter nal microcontroll er via the zm d44 101 p a rallel interfa c e a nd so me spi control re gist er in the re gister ban k. ZMD44101 single-chip 868mhz to 928mhz rf transceiver preliminary - march 2005 page 7 of 26 copyright ? 2005, zmd ag 4.2 serial peripheral interface (spi) 4.2.1 spi configuration the spi is configured via the spiconfig (r/w ) register. a standard based spi is used by default in slave m ode. certain registers can switch the interface to master mode to work with another slave. in that ca se the parallel microcontroller interface is used to control the ZMD44101. the interface provides t he standard lines miso, mosi, sck and ss. for write access the first bit of the first byte on mosi has to be ?0?. for read access the first bit of the first byte written to mosi has to be ?1?. ss (slave select) has to be ?0? when accessing the ZMD44101 through the spi. the ZMD44101 uses a data transfer protocol allowi ng single and multiple byte read/write access. all bytes are transmitted with the msb first and the lsb last. the protocol always starts by writi ng 2 bytes to the spi slave via the mosi line. the msb of the first byte is the read/write indicator. a high bit stands for read access and a low bit for write access. the read/write bit is followed by the length[6:0] descriptor n. it controls the length of the data frame d 0 [7:0] to d n-1 [7:0]. n hast to be in a range 1 to 127.the second byte is the address[7:0]. for tx/rx fifo access the address are 0x80 and 0x81 respectively. note that the tx fifo only allows write access and the rx fifo read access. in the case of register bank access a number of n bytes is read starting from address[7:0] up to address[7:0]+(n-1). in the case the fifo locations 0x80 or 0x81 are within this range they are skipped and the read/write access is continued at location 0x82. for write access the address[7:0] by te is followed by the data frame d 0 [7:0] to d n-1 [7:0]. in figure 4-2 the slave select signal ss is low during the complete writ e transfer. however it is also allowed to insert ss high gaps between each byte. in the read access protocol the data frame is shifted out by the slave on the miso line. before each data byte a ss high gap is required. similar to the write access a ss high gap can be inserted before the address[7:0] byte. timing parameters are listed in the following table. us mode eu mode parameter description min max min max tcp sck clock period 0.50 s 1.00 s tsc ss low to sck active edge 0.25 s 0.50 s tss ss high pulse with 1.00 s 2.00 s z m d4410 1 single-chip 868mhz to 928mhz rf transceiver p reliminar y - march 200 5 copyri ght ? 2 005, zmd ag page 8 of 26 d n- 1 [7 : 0 ] d 1 [7 :0] d 0 [7 :0] le ngt h[6: 0] (n) a[7: 0] d 0 [7 :0] ss mo si mi so ... ... ts s write a cce ss : rea d acc ess : w sc k sc k le ngt h[6: 0] (n) a[7: 0] mo si r ss d n- 1 [7 :0] ... ts c ts c tc p tc p tc p figure 4-2: t r ansfer protocol ( spi slav e mode), cpha= 0 cp ol= 0 ZMD44101 single-chip 868mhz to 928mhz rf transceiver preliminary - march 200 5 page 9 of 26 copyri ght ? 2 005, zmd ag add r ess d a [7 :0] rd wr ale ta s ta h ta d tds writ e d a t a td h w r ite ac ce ss : r e a d ac ce ss : add r ess d a [7 :0] rd wr ale ta s ta h r ead dat a x ta r tz d trv d 4.3 parallel interface the p a rallel i n terface con s ists of the bi -dire c tional da taaddress[7 : 0] bus an d the control in p u ts read (rd), write (wr) an d address lat c h en able (a le). the dire cti on of the da[7:0] bus is controlled by the rd in put. if rd is high da[7:0] are in input mode. setting rd lo w turn s da[7: 0 ] into output dire ction. the timing di agra m for re a d and write a c cess is sho w n bel ow. figure 4-2: p a rallel interface read/wr i te acc ess timing pa ram e ters a r e li ste d in the following table. us mode eu mode p a r a m e t e r d e s c r i p t i o n min max min max tas address setu p time 0 0 tah address hol d time 200 n s 200 n s tad address to da ta time 0 0 tds data setu p time 0 0 tdh data hold tim e 300 u s 600 u s tar address to rd low time 0 0 tzd high-z to data time 0 10 ns 0 10 ns trvd read lo w to valid data 400 u s 800 u s z m d4410 1 single-chip 868mhz to 928mhz rf transceiver p reliminar y - march 200 5 copyri ght ? 2 005, zmd ag page 10 of 2 6 5 registers the zm d44 1 01 ha s several regi ste r s fo r mac a nd p h y functio nal sup port. th e regi ster description shall give a brief o v erview only. a more detail ed de script io n can be fou n d in the use r s manual. the regi sters are acce ssi ble th roug h th e two inte rface p o rts. the hard wa re -mac registe r s p r ovi de a g r eat a d vantage fo r system impl e m entation in comp ari s o n to a mac impl em entation in a micro c o n troller only. especi a lly many system timing critical functi ons a r e impl e m ented in th e zmd44 101. most re giste r s ca n be refe rre d to in the ieee802.15.4 stand ard. 5.1 mac control + status register a d d r r e g i s t er name b i t s t y p e defau l t descri p t i o n 8' he0 irqreason 8 rw 0 interru pt reaso n 8' he1 irqmask1 8 rw 8' h00 interru pt mask[7:0] 8' he2 irqmask2 8 rw 8' h00 interru pt mask[15:8] 8' he3 irqmask3 7 rw 7' h00 interru pt mask[22:16] 8' h e 4 s p i c o n f i g 6 rw i 6' h 2 0 spi configurati on reg i ster 8' he5 spistart 1 rw s 0 spi start (master mode) 8' he6 spitx 8 rw 0 spi transmit b y te (master mod e ) 8' he7 spirx 8 r 0 spi receive b y t e (master mod e ) 8' he8 clkoutco n fig 8 rw 8' h29 clko pad co nfigur ation (d ef: normal mo de = 24mhz/4, slee p mode = 32.76 8khz) 8' hf 0 macco n trol 5 rw 5' h1f mac co ntrol c o mman d us ed b y firm w a re t o co ntrol th e hw -mac fsm transitio ns this contro l w o rd i s clear ed b y the intern al l ogi c after it w a s fe tched 8' hf 3 8' hf 1 mact xconfi g 4 rw 4' h2 mac transmit mode co nfig uration 8' hf 2 macr xco n fig 6 rw 6' h1a mac rx mod e config uratio n 8' hf 3 macbct rconfig 4 rw 4' h1 mac beac on track mode co nfi gurati on 8' hf 4 macscanm ode 2 rw 0 mac scan mo de (ed, pass i ve , active, orpha n) 8' hf 5 m a c o p m o d e 4 r 0 mac oper ating mode status register 8' hf 6 mact xstatus 7 r 0 mac transmit status register 8' hf 7 macr xstatus 8 r 0 mac rx status register 8' hf 8 macscanstatu s 8 r 0 mac scan status register 8' hf 9 macbct rstatu s 4 r 0 mac beac on track status regi ster 8' hf a m a c a u t o b c t xstatus 3 r 0 ma c auto be a c on tx status re gister 8' hf b macf ifostatus 4 r 0 mac tx/rx fifo s t atus register ZMD44101 single-chip 868mhz to 928mhz rf transceiver preliminary - march 2005 page 11 of 26 copyright ? 2005, zmd ag 5.2 mac timing registers addr register name bits type default description 8'hc0 t_rxdefer1 8 rw 8'h00 rx defer time [7:0] 8'hc1 t_rxdefer2 8 rw 8'h00 rx defer time [15:8] 8'hc2 t_rxdefer3 8 rw 8'h00 rx defer time [23:16] 8'hc9 t_scanduration1 8 rw 8'h00 scan duration (960*2^5) [7:0] 8'hda t_scanduration2 8 rw 8'h78 sc an duration (960*2^5) [15:8] 8'hcb t_scanduration3 8 rw 8'h00 sc an duration (960*2^5) [23:16] 8'hcc t_beaconinterval1 8 rw 8'h00 beacon interval (960*2^5) [7:0] 8'hcd t_beaconinterval2 8 rw 8'h78 beac on interval (960*2^5) [15:8] 8'hce t_beaconinterval3 8 rw 8'h00 beacon interval (960*2^5) [23:16] 8'hcf td_beaconinterval 4 rw 4'h4 t delta beacon interval generate irq 2^td_beaconinterval before next beacon 8'hd0 t_beaconscanduration1 8 rw 8'h00 beacon scan duration (960*2^6) [7:0] 8'hd1 t_beaconscanduration2 8 rw 8'hf0 beacon scan duration (960*2^6) [15:8] 8'hd2 t_beaconscanduration3 8 rw 8'h00 beacon scan duration (960*2^6) [23:16] 8'hd3 t_beaconscanstart1 8 rw 8'h0a beacon scan start (symbols before beacon interval end) (10) [7:0] 8'hd4 t_beaconscanstart2 3 rw 3'h0 beacon scan st art (symbols before beacon interval end) (10) [10:8] 8'hd5 t_sleep1 8 rw 8'h00 sleep time [7:0] 8'hd6 t_sleep2 8 rw 8'h00 sleep time [15:8] 8'hd7 t_sleep3 8 rw 8'h00 sleep time [23:16] 8'hd8 tdelta1 8 rw 0 superframe timing deviation between rfd and ffd [7:0] 8'hd9 tdelta2 3 rw 0 superframe timing deviation between rfd and ffd [10:8] used as additional guard time in cap/gts check 8'hda sfalignorder 4 rw 4'h0c superframe timing alignment order the rfd superframe timer is aligned to the estimated ffd timing every 60*2^sfalignorder symbols (12) z m d4410 1 single-chip 868mhz to 928mhz rf transceiver p reliminar y - march 200 5 copyri ght ? 2 005, zmd ag page 12 of 2 6 5.3 other ma c registers a d d r r e g i s t er name b i t s t y p e defau l t descri p t i o n 8' h9d msdul engt ht x 7 rw 0 mac pa yl oad ( m sdu) le ngth ( t x) 8' ha0 mhrf c1r x 8 r 0 mac hea der frame contro l b y te 1 (rx - last receiv ed frame) 8' ha1 mhrf c2r x 8 r 0 mac hea der frame contro l b y te 2 (rx - last receiv ed frame) 8' ha2 mhrsqu nbr x 8 r 0 mac hea der s equ enc e numb e r (rx - last re ceive d frame) 8' ha3 mpdu len gthr x 7 r 0 mpdu l engt h (rx - last rece iv ed frame) 8' ha6 macf ramepe n d 6 rw 0 numb e r of frames pen di ng in rx f i f o queu e, reset b y soft w a r e 8' h a 7 m a c s u p erfram e o r d e r 4 rw 5 mac superfra m e order (so) 8' ha8 maccape nd 4 rw 15 last slot in cap 8' h a 9 m a c g t s s t a r t 4 rw 1 0 1st slot of the gt s 8' h a a m a c g t s l e n g t h 4 rw 0 gt s length in slots (zero no gt s) 8' h a b m a c t otal t i mef f d 1 8 r 0 current totaltim e [7:0] (f f d mode) i n multip le of 32khz cloc k 8' h a c m a c t otal t i mef f d 2 8 r 0 current totaltim e [15:8] (f f d mode) 8' h a d m a c t otal t i mef f d 3 8 r 0 current totaltim e [23:16] (f f d mode) 8' h a e m a c t otal t i merf d 1 8 r 0 curr ent totaltim e [7:0] (rf d mode) 8' haf m a c t otal t i merf d 2 8 r 0 curr ent totaltim e [15:8] (rf d mode) 8' h b 0 m a c t otal t i merf d 3 8 r 0 curr ent totaltim e [23:16] (rf d mode) 8' hb1 maccurre nts y mbolt i me1 8 r 0 current sup e rframe time [7:0] 8' h b 2 m a c c u r r e nts y mbolt i m e 2 8 r 0 current superframe time [15:8] 8' h b 3 m a c c u r r e nts y mbolt i m e 3 8 r 0 current superframe time [23:16] 8' hb4 maccurre nt sl ot 4 r 0 current slot 8' h b 5 m a c b e a c onr xt i m e 1 8 r 0 timestamp[ 7:0] of the last receive d be acon 8' h b 6 m a c b e a c onr xt i m e 2 5 r 0 timestamp[12: 8] of the last receive d be acon 8' hb7 macscane d 8 r 0 maximum ed v a lu e from the ed scan 8' hbe macma x l o stbeaco n s 4 rw 4 numb e r of max lost beaco n s b e fore a s y nc lo ss is indic a ted 8' hbf macs yncl oss 4 r 4 numb e r of lost beac ons 8'h75 crcfai l1 8 r 0 numb e r of cr c failur e s [7:0] 8 ' h 7 6 c r c f a i l 2 6 r 0 numb e r of cr c failur e s [13:8 ] 8' h77 f r amer xco unt 1 8 r 0 numb e r of rece ived frames [7: 0 ] 8' h 7 8 f r amer xco unt 2 6 r 0 numb e r of rece ived frames [1 3:8] ZMD44101 single-chip 868mhz to 928mhz rf transceiver preliminary - march 2005 page 13 of 26 copyright ? 2005, zmd ag 5.4 mac header registers addr. register name bits type default description 8'h82 mhrfc1tx 8 rw 0 mac header frame control byte1(low byte) (tx) 8'h83 mhrfc2tx 8 rw 0 mac header frame control byte2(high byte) (tx) 8'h84 mhrsqunbtx 8 rw 0 mac header sequence number (tx) 8'h85 mhrdstpanid1tx 8 rw 0 mac header de st. pan identifier byte1(low byte) (tx) 8'h86 mhrdstpanid2tx 8 rw 0 mac header de st. pan identifier byte2(high byte)(tx) 8'h87 mhrdstaddr16_1tx 8 rw 0 mac header dest. 16bit address byte1(low byte) (tx) 8'h88 mhrdstaddr16_2tx 8 rw 0 mac header dest. 16bit address byte2(high byte) (tx) 8'h89 mhrdstaddr64_1tx 8 rw 0 mac header dest. 64bit address byte1(low byte) (tx) 8'h8a mhrdstaddr64_2tx 8 rw 0 mac header dest. 64bit address byte2 (tx) 8'h8b mhrdstaddr64_3tx 8 rw 0 mac header dest. 64bit address byte3 (tx) 8'h8c mhrdstaddr64_4tx 8 rw 0 mac header dest. 64bit address byte4 (tx) 8'h8d mhrdstaddr64_5tx 8 rw 0 mac header dest. 64bit address byte5 (tx) 8'h8e mhrdstaddr64_6tx 8 rw 0 mac header dest. 64bit address byte6 (tx) 8'h8f mhrdstaddr64_7tx 8 rw 0 mac header dest. 64bit address byte7 (tx) 8'h90 mhrdstaddr64_8tx 8 rw 0 mac header dest. 64bit address byte8(high byte) (tx) 8'h91 mhrsrcpanid1tx 8 rw 0 mac header source pan identifier byte 1(low byte) (tx) 8'h92 mhrsrcpanid2tx 8 rw 0 mac header source pan identifier byte 2(high byte (tx) 8'h93 mhrsrcaddr16_1tx 8 rw 0 mac header source 16bit address byte 1(low byte) (tx) 8'h94 mhrsrcaddr16_2tx 8 rw 0 mac header source 16bit address byte 2 (tx) 8'h95 mhrsrcaddr64_1tx 8 rw 0 mac header source 64bit address byte 1 (tx) 8'h96 mhrsrcaddr64_2tx 8 rw 0 mac header source 64bit address byte 2 (tx) 8'h97 mhrsrcaddr64_3tx 8 rw 0 mac header source 64bit address byte 3 (tx) 8'h98 mhrsrcaddr64_4tx 8 rw 0 mac header source 64bit address byte 4 (tx) 8'h99 mhrsrcaddr64_5tx 8 rw 0 mac header source 64bit address byte 5 (tx) 8'h9a mhrsrcaddr64_6tx 8 rw 0 mac header source 64bit address byte 6 (tx) 8'h9b mhrsrcaddr64_7tx 8 rw 0 mac header source 64bit address byte 7 (tx) 8'h9c mhrsrcaddr64_8tx 8 rw 0 mac header source 64bit address byte 8(high byte) (tx) 5.5 phy registers addr register name bits name remarks 8?h00 rpcc 8 phycurrentchannel re gister rf channel selection 8?h05 rtxm 6 transmitter mode register transmitter baseband filtering, output port select, and pa output level controls 8?h0e ragcl 8 agc level register indicates agc level in closed loop mode and sets agc gain in open loop mode the system description in paragraph 8 gives inform ation about the registers in the phy. many more registers can be accessed and programmed/read but are not essential for typical applications. all phy registers are written through mac commands as defined in the ieee 802.15.4 standard. they can be overridden. all phy registers are read and write capable. every register can be written to and read from at any time during operation by the microcontroller thr ough either the parallel or sp interface. a detailed description of all register will be available as an application note. z m d4410 1 single-chip 868mhz to 928mhz rf transceiver p reliminar y - march 200 5 copyri ght ? 2 005, zmd ag page 14 of 2 6 q1 c1 c2 c6 c7 c8 r2 r1 z m d 4410 1 1 48 12 13 24 25 36 37 wr rd dv dd _3. 3 dv s s dv dd ale av d d av ss rt c1 rt c2 nc nc ss ir q gpd dv dd_3. 3 dv dd rsn dv dd nc nc av d d lp f 2 lp f 1 mo si miso sc k da[ 0 ] da[ 1 ] da[ 2 ] da[ 3 ] da[ 4 ] da[ 5 ] da[ 6 ] da[ 7 ] clk o xt al 2 xt al 1 av d d rf o av ss rf i o av ss av d d av ss av d d nc nc q2 c4 c5 spi m i c r o c on tr ol l e r in ter f a c e 11 r eset inte r r upt p o we r d o wn 2. 4v o l t 3.3 v ol t c3 c1 0 c1 1 6 application circuit ? external components the zm d4 41 01 requi re s v e ry few external comp one nts all o win g f o r a sm all m odule fo rm fa ctor and lo w bill of materia l co sts. figu re 6.3 de pict s whi c h comp o nents are re q u ired i n a typi cal a pplicatio n. aside fro m these com p o nents only a microcontroll er, with it?s e x ternal comp onent s, is ne eded. thi s m i cro c o n troll e r has to m a int a in and co ntrol the a ppli c ation sp ecif i c software d epen dent fun c tion s a s def ined by the zigbee tm standard. the st anda rd mi cro c ontrolle r inte rf ace s a r e de scribe d in pa ragra ph 4.3. figure 6.1 - external com pone nts in a typical zm d44 101 ap plicati o n componen t v a l u e componen t v a l u e c1 15pf, 5%, smd c8 15pf, 5%, smd c2 15pf, 5%, smd c10 >10 0uf ii 10 0nf, 6.3v, decou pling c3 22pf, 5%, smd c11 >10 0uf ii 10 0nf, 6.3v, decou pling c4 43pf, 5%, smd r1 12kohm, 5%, smd c5 43pf, 5%, smd r2 3.9ko h m, 5%, smd c6 5.6pf, 5%, smd q1 32.768 khz, watch crystal type c7 220pf, 5%, smd q2 24mhz, 4 0p pm ZMD44101 single-chip 868mhz to 928mhz rf transceiver preliminary - march 2005 page 15 of 26 copyright ? 2005, zmd ag 7 ZMD44101 system performance summary note: simulated system performance based on ieee 802.15.4 standard. parameter value operational specifications supply voltage +2.2v to +2.7v (typical +2.4v) digital io voltage +3.0v to +3.6v (typical +3.3v) temperature range -40c to +85c frequency of operation 868mhz to 870mhz (eu) and 902mhz to 928mhz (us) typical supply current (tx) 32ma typical supply current (rx-synchronization) 31ma typical supply current (rx-normal) 28ma typical supply current (sleep mode) 2a system specifications standard basis ieee 802.15.4/d18 compliant spreading technique direct sequence spread spectrum (dsss) modulation type binary phase shift keying (bpsk) data rate burst 20kbits/s (eu) and 40kbits/s (us) pn code 15-chip m-sequence processing gain 12db chip rate 300kbit/s (eu) and 600kbit/s (us) rf bandwidth 600khz (eu) and 1200khz (us) rf channel spacing 2mhz (ieee 802.15.4 compliant) overall crystal accuracy 40ppm architecture receiver (rx) direct down-conversion transmitter (tx) direct up-conversion phase locked loop (pll) sigma-delta fractional-n block specifications rf_pll frequency resolution 732hz tx output power 0dbm (to 50 ) tx spurious emissions etsi (en 300 220) and fcc (part 15) compliant rx sensitivity -100dbm@per<1% rx maximum usable input level -20dbm rx selectivity/blocking performance i eee 802.15.4 compliant + etsi rx class 2 general parameters package 48-pin qfn (=mlf tm microleadframe) esd protection >2kv (human body model ? hbm) interface spi and parallel external components 24mhz & 32.768khz xtal, p ll loop filter (rc), antenna, microcontroller process technology 0.25m cmos z m d4410 1 single-chip 868mhz to 928mhz rf transceiver p reliminar y - march 200 5 copyri ght ? 2 005, zmd ag page 16 of 2 6 ad c lp fil t er ag c w i t h l p f ln a i q rx rf pll tx da c p a m i xer xta l os c freq uen c y doub ler pf d 90 0m h z 48 m h z 24 m h z 24 m h z d i g i t a l p a r t digital part ad c maste r bias lp f xta l os c 3 2 . 7 68 kh z por ch ann e l g a in 8 system description 8.1 general block diagram figure 8.1 - integrate d an alog phy lay er blo ck di ag ram ZMD44101 single-chip 868mhz to 928mhz rf transceiver preliminary - march 200 5 page 17 of 2 6 copyri ght ? 2 005, zmd ag m a c control phy rx ma c rx ph y t x ma c t x reg . bank tx d a t a p a t h - phy f r am e - by te to bit - dif f . encode - s p readi ng - pulse s h ape rx data p a t h - e d - c a rr i e r s ense - ac qui s i ti on - notc h - dow n conv er t - des pread - dif f . dem od - bit t o by te ph y t x c o n t r o l phy rx co ntrol pow e r co ntrol tx f i f o / rx fifo (2) rx fifo (1) crc crc ma c con t rol rt c beac o n /sy n c ti mi n g gts ti mi n g in ter fa c e spi par a llel cs m a irq ma c framer sym b o l ti m e r sca n ti mi n g he ad e r dec o de ac k r e q , s eqnum , fr am et y p e clo c k co ntrol gp d ba d f r a m e cou n t e r ac k fr am e p e r/be r figure 8.2 - integrate d digi tal phy and mac layer bl ock diag ram 8.2 receiver chain the re ceive r of the zmd44 101 u s e s a di rect -conv ersi on archite c ture (ze r o-if a r chitecture). the re ceive r path co nsi s ts of a 900mhz low-noi se a m plifier (l na ) and a mixe r, followed b y the analo g baseba nd. it contai ns m u lti-stag e prog rammabl e gai n am plifiers, low-pa ss filte r se ction s an d analog -to- digital conve r ters (a dc). all remai n i ng fun c tion s are ca rri ed out in the digital do m a in in cludi ng synchro n ization, de -sprea ding and de modulatio n a s well as the agc lo op co ntrol. to exte nd the dyna mi c rang e furthe r, the lna and mixer gain ca n be adju s ted in the agc loop. in normal op eration mo de , the user or the mac starts the recepti on usin g the default regi st er value s . all control sig nal s (timing, po wer-d o wn) a r e set automat ically. one re ceiver regi ster setting can be i m porta nt for re ceiver op eration (rag cl). this is descri bed i n para g raph 8. 2.1. beside s this re giste r there are r egi sters which a r e u s ed in b o th, transmit and receive mode. z m d4410 1 single-chip 868mhz to 928mhz rf transceiver p reliminar y - march 200 5 copyri ght ? 2 005, zmd ag page 18 of 2 6 8.2.1 ragcl - agc level register b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 0 1 1 1 1 1 1 1 1=g a in high, 0=g a in lo w the regi ster can be u s e d to read the a g c level ba ck to the mi croco n trolle r at any time du ring re ceive r operation. t h is way info rm ati on a bout t he sign al stre ngth can be derived by th e micro c o n tro ller. th e hi gh gain default value (hex7f ) tog e ther with the digital pea k d e tectio n fun c tion en sures fa st se ttling time b y redu cin g the gain in ste p s to a usabl e si gnal level for the digital sig nal pro c e s sin g insid e the zmd44 101. 8.3 transmitter chain a dire ct-con versio n a r chi t ecture is u s ed for the t r ansmitte r of the zm d44 1 01. th e d e s ign is f u lly differential. o n ly the power amplifier (pa) output is sin g le-e nde d. no external bal un is re qui red . in normal op eration m ode , the user or the mac sta r ts the tran sm issi on u s ing t he default re gister val u e s . all control sig nals (timi ng, pow er-do w n ) are set autom atically. optionally two default regi ster setting s of the tr an smitter ca n be cha nge d by writing to th e trans m itter mode regi st er ( rtxm ). b y default, the pa drives 0 d bm (1m w) t o a 50 oh m off-chip l oad. this outp u t power can be chan ged b e twee n 0dbm a nd -21 d bm. 8.3.1 rtxm - transmi tter mode register b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 d e f a u l t 0 0 0 0 0 0 0 0 0 dbm output powe r 0 0 0 0 x x x x -7 dbm outpu t power 0 0 0 1 x x x x -14 dbm outp u t powe r 0 0 1 0 x x x x -21 dbm outp u t powe r 0 0 1 1 x x x x normal op era t i o n 0 0 x x x 0 0 0 carrie r only modulatio n 0 0 x x x 0 1 0 con s tant ?0? d a ta tran smit 0 0 x x x 1 0 0 rfio is output 0 0 x x 0 x x x rfo i s outpu t 0 0 x x 1 x x x ZMD44101 single-chip 868mhz to 928mhz rf transceiver preliminary - march 200 5 page 19 of 2 6 copyri ght ? 2 005, zmd ag tx-rx-switch configuration rxio rfio txio rfo txo lna pa furthe rmo r e, by default the re ceiver i n put and the tran smitter output u s e the sam e pin ( rfio ). the inte grate d anten na switch di sconn e c ts th e respe c tive co mpone nts in transmit and receive mode. by changi ng bit3 in the rtxm regi ster, the transmitter us es rf o as the output pin. thi s allows to u s e an exte rnal power amplifier fo r highe r output po we r a n d extended ran ge (see left figure). the anten na has to be conn ecte d via an external 22 pf capa citor. 8.4 rf phase locked lo op a fractio nal-n phase l o cked l oop (pl l ) a r chite c ture is used. all functio n s are in teg r ated on chip exce pt for the lo op filter. the ex ternal lo op fil t er ci rcuitr y i s de picte d in figure 8.3. the 24 mhz cry s tal (see para g raph 8. 5) provide s the referen c e fr eque ncy for b o th the eu- a nd us-ban ds. 5. 6pf 5 % 220 pf 5% 15pf 5% 3. 9k 5% 12k 5% lp _c p lp _ v c o figure 8.3 - pll-l oop filter in norm a l o p e ration mod e , the user se ts the freque nc y chan nel of the rf pl l pri o r to t r a n smi ssi on or reception. all co ntrol si gnal s (t imin g, po we r-d o w n) a r e se t automati c a lly by writing to the phycu rrentchann el regi ster (rp c c), b u t ca n b e overwritten fo r non-stan da rd appli c atio ns. the data rat e (eu: 20k b it/s and us: 40kbit/s ) is adj usted autom atically acco rdin g to the sele cted chan nel. the cha nne l numbers are defined by the ieee 802. 15.4 standard. figure 8.4 illustrate s the channel all o cation in t he 900m hz b a n d . table 8.1 d epict s the rp cc p r og ram m ing in the z m d44 101. 86 8 . 3 m h z ch ann e l 0 ch ann e l s 1- 1 0 92 8 m h z 90 2 m h z 2 m h z figure 8.4 - cha nnel allo cation in the 9 00mhz ba nd z m d4410 1 single-chip 868mhz to 928mhz rf transceiver p reliminar y - march 200 5 copyri ght ? 2 005, zmd ag page 20 of 2 6 b a n d c h a n nel sel e c t (rp cc reg.) as per ieee802.15.4 chan nel (mh z ) channel (bin) (rpl c1/2 r e g.) c h annel ( d ec) sel_su bban d (rplm reg.) europ e a n 0 8 6 8 . 3 0010 1101 110 1110 1 1174 1 0 1 u s a 1 9 0 6 1100 0000 000 0000 1 4915 3 1 0 u s a 2 9 0 8 1101 0101 010 1010 1 5461 3 1 0 u s a 3 9 1 0 1110 1010 101 0101 1 6007 5 1 0 u s a 4 9 1 2 0000 0000 000 0000 0 0 1 1 u s a 5 9 1 4 0001 0101 010 1010 1 5 4 6 1 1 1 u s a 6 9 1 6 0010 1010 101 0101 1 1092 3 1 1 u s a 7 9 1 8 0100 0000 000 0000 1 1638 5 1 1 u s a 8 9 2 0 0101 0101 010 1010 1 2184 5 1 1 u s a 9 9 2 2 0110 1010 101 0101 1 2730 7 1 1 u s a 1 0 9 2 4 1000 0000 000 0000 1 3276 9 1 1 table 8.1 ? channel select regi ster programmi ng according to the ieee 802.15.4 standard 8.5 reference cry s tal os cillator (24 m hz) a two (2 ) pin pierce o s cilla tor with on -ch i p bia s in g re sistor is de sig ned to prov id e the ne ce ssary refere nce freque ncy at 24mhz. thi s freque ncy is use d for digit a l clo ck sup p l y , timing calculation s as well as for the pll that gen erate s the rf ca rrie r fre q uen cy. for t he re ceive m ode s the inte rnal circuitry doubl es the referen c e fre quen cy in order to achie v e the digi tal processin g spee d duri n g cod e acq u i sition. this oscillator i s o n ly active in idle, tran smit and receive power mo de s. the user ca n also p r ovide an exte rnal 2 4 mhz clo c k re feren c e on xtal1. thi s external clo c k h a s to have 24mhz at a d u ty cycle of 1 : 1 and a n a c cura cy of 4 0 p p m. provided this case no 24mhz cry s ta l is requi red betwe en xtal1 and xtal 2 and xtal2 is not co nne cted. whe n the int e rnal o scill ator i s u s e d c4 and c5 a r e required as lo ad cap a cito rs for th e p a rall el re so nan ce cry s tal. the value s c4 an d c5 are different for any specifi c enviro n ment. the o v erall load ca pacita n ce is comp osed of the a c tual v a lue s of c4 and c5 a s well as th e p a rasitic val u e s of the pcb l a yout and th e internal p a ra sitic capa citan c e of the zmd44 101, whi c h is 0.65pf o n each pi n. the total load cap a cita nce has to m a tch the re comm ende d typical load capa cit ance p r ovide d by th e cry s tal m anufa c turer. fo r a recomme nde d 97smx2 4 0 22b crystal (smi) the loa d capa citan c e is 22p f 0. 5%. any deviation on thi s system p a rt will re sult in large d e viatio n on the ca rri er freq uen cy and outp u t sp ectru m . this clock is available for external u s e on pin 36, clko. it c an be us ed to s u pport a microc ontroller. duri ng p o wer-do wn a nd sl eep mo de th e micro c ontroller clo ck i s swit che d to 3 2 .768 khz o r to sele ctabl e fraction s of 3 2 .768 khz fo r re du ced current co nsu m pti on. t h is ensure s th e microcontroll er ha s a cl ock sign al duri n g powe r -down and therefo r e can corre c t l y wake up from the powe r-d own state. during all other st ates t he 24mh z cl o ck o r selecta b le fractio n s of 24mhz ca n be used on clko. xt al 2 xt al 1 24 m h z c4 c5 figure 8.5 - 24mh z crysta l oscill ator ? e x ternal co mp onent s ZMD44101 single-chip 868mhz to 928mhz rf transceiver preliminary - march 200 5 page 21 of 2 6 copyri ght ? 2 005, zmd ag 8.6 lo w po w e r cr y s tal oscillator (3 2.768khz) the 32.7 6 8 k hz cry s tal o s cillator i s d e signed fo r extreme lo w p o w er ope ratio n as it al way s ru ns wh en power i s appl ied to th e de vice. th e o s cillator p r ovid es th e time referen c e for the o n -chip re al time clo ck. the oscillato r utilizes an a m plitude cont rolled two (2) pin pierce oscillator with on-chip bia s in g resi stor. th e same a s de scrib ed for the 24mhz o scill ator in pa rag r aph 8.5 is vali d for the load cap a cita nce. rtc2 rtc1 3 2 . 768 kh z figure 8.6 - 32.768khz crystal oscillato r ? external components this clock is available for external u s e on pin 36, clko. it c an be us ed to s u pport a microc ontroller. duri ng p o wer-do wn a nd sl eep mo de th e micro c ontroller clo ck i s swit che d to 3 2 .768 khz o r to sele ctabl e fraction s of 3 2 .768 khz fo r re du ced current co nsu m pti on. t h is ensure s th e microcontroll er ha s a cl ock sign al duri ng power-do w n and ther efore can corre c tly wake up fro m the powe r -down state. 8.7 clko - clock output configuration this regi ste r i s pa rt of the mac control and status re gister s. th e clock on the cklo pin ca n be configu r ed according to t he followi ng t able for external micro c ont rolle r clo c k suppo rt. pin36 can di re ctly drive a clo c k input up to 4 m a. c l k o u t c o n f i g [ 7 : 6 ] c l k o u t c o n f i g [ 5 : 4 ] c l k o u t c o n f i g [ 3 : 2 ] c l k o u t c o n f i g [ 1 : 0 ] value r t c d i v ( m ) c l k 2 4 d i v ( n ) normalmo de c l k sleepmo decl k 0 1 1 o f f o f f 1 2 2 3 2 k / m 3 2 k / m 2 4 4 2 4 m / n 2 4 m / n 3 8 8 the table i s to be read a s follows. example defa u lt: the cl ko utconfig(@d e fau l t)=8' b00 101 0 01, com pares to "0,2,2,1". that me an s: m=1, n=4, durin g norma l mod e (everything but no t slee p or g p d) clk o i s 24mhz/4 =6m h z, an d duri n g slee p mode clko is 3 2 .768 khz. z m d4410 1 single-chip 868mhz to 928mhz rf transceiver p reliminar y - march 200 5 copyri ght ? 2 005, zmd ag page 22 of 2 6 8.8 pow e r management the zm d44 1 01 ha s five di fferent mod e s of po we r m anag ement. these mo de s are user con f igurabl e an d controlled by the external microcontroll er. the po we r mode s are as follo ws: ? tx/rx : tx or rx is ac tive. ? idle: tx/rx are po we re d down but the 24mhz crystal oscill ator remains on. ? sleep : all circuits are switch ed off e x cept the 32 .768khz rt c for accu ra te time refe rence. powe r co nsu m ption is red u ce d to 2a (typical). ? pow e r dow n : t h e z m d44 101 en ters into po wer do wn by setting th e g l obal po we r do wn (gpd) func tion. ? power off: the sup p l y voltage is swit che d off externally. the zmd4 410 1 has a power o n re set (po r ) function. note: t he zmd4 410 1 contain s inte rnal ma ste r bi as ci rcuitry. no adju s tme n ts o r extern al ci rcuitry a r e requi re d for a c curate o p e r a t ion. ZMD44101 single-chip 868mhz to 928mhz rf transceiver preliminary - march 200 5 page 23 of 2 6 copyri ght ? 2 005, zmd ag 9 mechanical specifications 9.1 packag e 48pin qf n p a ckag e z m d4410 1 single-chip 868mhz to 928mhz rf transceiver p reliminar y - march 200 5 copyri ght ? 2 005, zmd ag page 24 of 2 6 d i m m i n t y p m a x n o t e s a 0 . 8 0 1 . 0 0 a 1 0 . 2 0 3 r e f b 0 . 1 8 0 . 2 5 0 . 3 0 applies to metallized terminal and is measured between 0.25mm an d 0.30mm from terminal tip. d 7 . 0 0 b s c e 7 . 0 0 b s c d 1 5 . 0 4 5 . 2 4 e 1 5 . 0 4 5 . 2 4 e 0 . 5 0 b s c l 0 . 4 3 0 . 5 3 0 . 6 3 l1 0.10 rep r e s ent s t e rmin al full b a ck from pa ckag e edge up to 0.1mm is acce ptable. l 2 0 . 3 0 0 . 4 0 0 . 5 0 p 4 5 o bsc a a a 0 . 1 5 c c c 0 . 1 0 note s: 1. dimen s io ns a nd tolera nces conform to asme y14.5m-199 4 2. all dimensi o ns are in millim et ers. angles are in degrees. 3. co-plan a rity applie s to the expose d hea d slug a s well as the termin al. 4. radi us in terminal is optio nal. ZMD44101 single-chip 868mhz to 928mhz rf transceiver preliminary - march 200 5 10 list of abbreviations adc analog -to-dig i tal converte r aes advanc ed enc r yption standard agc automatic ga n control ber bit error rate bpsk binary phase shift keying cmos compl e me ntary metal oxide silicon cr c cod e re dun dan cy che c k csma car r ie r sen s e multiple access dac digital-to -ana log co nverte r db de cibel dsss d i r e c t se q uen c e spr e ad spectrum ed energy detection esd elec tros tatic disc harge etsi europ ean tel e com m uni cat i ons standards in stitute eu europe fcc fede ral com m unication s commi ssion fifo firs t in firs t out gpd gener a l power d o w n gts guarantee d time slot ieee institute of electri c al an d electro n ics engine ers if intermedi ate freq uen cy irq interrupt reques t ism industri a l- sci entific medi ca l kbit/s kilobit per se con d khz kilohert z lna low noi s e amplifier los line of sig h t lp filter low pa ss filt er mac medium acce ss cont rolle r miso ma s t er - i n- slave - o u t, mosi master-out-s lave-in mhz megah ert z mlf micro lea d frame per pac k et error rate phy phys ic al (lay er) pll phase l o cke d loop qfn quad flat pa ck rf radi o fre que ncy rtc real tim e cl oc k rx re ceiv er spi serial peri ph eral interfa c e ss slave-sele ct (refe rs to cs=chip selec t ) tx tran smitter us united states xtal crys tal 11 references ? ieee 802.15.4-2003 standard: ?ieee st andard for part 15.4: wirel e ss medium access control (mac) and p h ysical layer (phy) spe c ifi c ation s for lo w rate wirel e ss person al area netwo r ks (l r- wpans)?. download: http ://standards.ieee.org/getiee e802/download/802.15.4-2003.pdf ? etsi en 300 220-1 v1.3.1 (200 0-09) ? fcc pa rt 15, de cemb er 1 8 2001 page 25 of 2 6 copyri ght ? 2 005, zmd ag z m d4410 1 single-chip 868mhz to 928mhz rf transceiver p reliminar y - march 200 5 the info rmation f u rnished he re b y zmd is believed to be correct an d accurate as of the publication d a te. ho wever, z m d shall not be liable to any thir d part y fo r an y d a mages, includin g but no limit ed to personal injury, prop ert y dam age, loss of profits, loss of u s e, interruption o f bu siness or indirect, special, inciden tal, or conseque ntial damages of an y kind in con nection w i th or a r ising o ut of the fur n ishing, per formance, or use of the tec hnical data. no obligation or liability to any thir d par ty shall ar ise or flow out of zm d's rendering t e chnical or other se rvices. for furthe r information zmd phon e: 858- 67 4-84 33 f a x: 858-67 4-80 71 e-mail: w i r e les s @zmda.com zmd 153 73 inn o vati on driv e suite 115 san di ego, ca 92128 http:// w w w . zmd.biz zmd a g grenzstrasse 28 d-01 109 dr esd en tel.: +49 351 88 22 928 fax: +4 9 351 88 22 666 products sold b y zmd are covere d exclusively b y t he zm d standa r d w a r r ant y, pate n t indemnificati on, and other p r ovisions appeari ng in zmd standa rd "te r ms of sale" . testing and ot her qualit y c ontr o l techniques ar e used to t he e x tent zmd deems necessar y to support this w a r r ant y . e x cept w h ere man dated b y governme n t requirements, t e sting of all parameters of each product is no t necessarily perfo rmed. zmd makes no w a rra nt y (exp ress, statut or y , implied and/or b y description), including w i thout limitat io n an y w a rra nties of merchantability an d/ or fitness for a p a rticular pur pose , regarding the information set fort h in the material s per taining to zmd pr oducts, or rega rding the f r eedom of an y p r oducts descri bed in the materials from patent and/o r other inf r ingem ent. zmd rese rves the right to dis c ontinue produc tion and chang e specifications and pric es, make corrections, modifications, enhancements, improvements and other changes of its products and se rvice s a t an y time w i tho u t notice. zmd products are intended for us e in commercial applications. applications requiring e x tend ed tempe r ature range, unusu a l environmenta l requirements, or high reliability a pplications, such as milit ary , me d i cal life-support or lif e-sustaining equipment, are specif ica lly not recommended without additional mutually ag reed upon processing b y zmd fo r such applications. zmd assumes no liability fo r application assistance or custom er pro duct design. custome r s are respo n sible for their pr oduct s and applications using zm d components. pr i n t da te: 30. 03. 20 05 11:2 9 copyri ght ? 2 005, zmd ag page 26 of 2 6 |
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